The present invention relates to a method of forming patterned metal films wherein the pattern includes submicron-dimensioned features and is practically useful in integrated circuit semiconductor device manufacture. The present invention especially adapted for use in "back-end" processing for forming in-laid metallization patterns.
The escalating requirements for high density and performance associated with ultra large-scale integration (ULSI) semiconductor device wiring are difficult to satisfy in terms of providing submicron-dimensioned (e.g., below 0.18 .mu.m), low RC time constant metallization patterns, particularly wherein the submicron-sized metallization features such as vias, contact areas, grooves, trenches, etc., have high aspect (i.e., depth-to-width) ratios due to microminiaturization.
The present invention is applicable to various types of semiconductor devices, such as the type illustrated in FIG. 1 comprising a semiconductor substrate, usually of doped monocrystalline silicon (Si), having at least one active device region or component (e.g., an MOS type transistor, a diode, etc.) formed therein or thereon, and a plurality of sequentially formed inter-layer dielectrics (ILDs) and patterned conductive layers (METAL) formed therein and/or therebetween. An integrated circuit is formed therefrom containing a plurality of patterns of conductive lines separated by interwiring spacings, and a plurality of interconnection lines, such as bus lines, bit lines, word lines, and logic interconnect lines. Typically, the conductive patterns of substantially vertically spaced apart metallization layers are electrically interconnected by a substantially vertically oriented conductive plug (VIA) filling a via hole formed in the ILD separating the metallization layers, while another conductive plug filling a contact area hole establishes electrical contact with an active region (e.g., a source/drain region of an MOS type transistor) formed in or on the semiconductor wafer substrate. Conductive lines formed in groove or trench-like openings in overlying dielectric layers extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type as illustrated in FIG. 1 and fabricated according to current technology may comprise five or more levels of such metallization in order to satisfy device geometry and miniaturization requirements.
Electrically conductive films or layers of the type used in "back-end" semiconductor manufacturing technology as required for fabrication of devices such as above described and illustrated in FIG. 1 typically comprise a metal such as titanium, tantalum, tungsten, molybdenum, aluminum, chromium, nickel, cobalt, palladium, silver, gold, copper, and their alloys. However, conventional methodology for performing "back-end" metallization processing utilizing any of the enumerated metals presents several disadvantages and drawbacks. Specifically, such conventional "back-end" processing is complex, difficult, costly, time consuming, and incurs a significant reduction in interconnection reliability and product yield as feature sizes decrease and the number of metallization levels increases. For example, a typical damascene-type process performed according to the conventional art for forming a single via/metallization pair can involve over 40 separate processing steps, including, inter alia, formation of a photoresist layer on a first dielectric layer; selective exposure of the photoresist through a mask; development of the photoresist; selective etching of the resist-coated dielectric layer to form a via hole pattern therein; filling of the via holes with metal, deposition and planarization of a second dielectric interlayer; photoresist formation thereon; pattern-selective exposure and development to form a pattern of openings therein corresponding to the desired metallization pattern; etching of the second dielectric layer to form a recess pattern therein corresponding to the desired metallization pattern; filling of the recesses with the selected metal, including formation of a blanket or overburden layer of excess thickness to ensure complete filling of the recesses; removal of the blanket or overburden layer; and planarization of the dielectric layer surface having the in-laid metallization pattern. Inasmuch as formation of each additional layer pair of vias/patterned metallization adds an additional approximately 40 process steps, it is evident that repetition of the above-described sequence of processing steps up to, e.g., 15 times, for forming high integration density, multi-metallization level semiconductor devices, entails significant cost, increased likelihood of occurrence of reliability problems, and reduced product yield. Furthermore, non-damascene type processes for forming in-laid metallization patterns, e.g., comprising blanket deposition of metal layers followed by selective removal thereof to define desired metallization patterns therein, dielectric gap-filling, and planarization are equally difficult, complex, expensive, and result in reduced reliability and product yield.
Thus, there exists a clear need for an efficient, simplified method for forming in-laid, "back-end" metallization patterns at low cost and with increased reliability and product yield. Specifically, there exists a need for an improved method for forming such metallization patterns in submicron-sized dimensions, for forming contacts, vias, and interconnect routings, which method is fully compatible with conventional process flow and methodology in the manufacture of ultra large-scale integration semiconductor devices.
The present invention fully addresses and solves the above described problems and drawbacks attendant upon conventional processes for manufacturing integrated circuit semiconductor devices requiring multiple metallization levels, particularly in providing a dramatic, very significant reduction in the number of requisite processing steps (i.e., from about 40 to about 6 for each via/metallization pair), thereby significantly reducing manufacturing costs, increasing product reliability and yield, and significantly increasing production throughput.